Chip package and manufacturing method thereof

ABSTRACT

A chip package includes a chip, an insulating layer, a flowing insulating material layer and conductive layer. The chip has a conductive pad, a side surface, a first surface and a second surface opposite to the first surface, which the side surface is between the first surface and the second surface, and the conductive is below the first surface and protruded from the side surface. The insulating layer covers the second surface and the side surface, and the flowing insulating material layer is disposed below the insulating layer, and the flowing insulating material layer has a trench exposing the conductive pad protruded form the side surface. The conductive layer is disposed below the flowing insulating material layer and extended into the trench to contact the conductive pad.

RELATED APPLICATIONS

This application claims priority to U.S. provisional Application Ser.No. 62/164,218, filed May 20, 2015, which is herein incorporated byreference.

BACKGROUND

1. Field of Invention

The present invention relates to a chip package and a manufacturingmethod thereof.

2. Description of Related Art

Along with the necessary of electronic devices toward lighter and morecompact, the semiconductor chip corresponding to the electronic devicehas a reduced size and increased wiring density. Therefore, it is moredifficult and challenging to fabricate a semiconductor chip package inthe subsequent process for the semiconductor chip. Wafer-level chippackage is a method of packaging the semiconductor chip, which meansthat all the chips are packaged and tested after completion ofmanufacturing these chips on the wafer, and then the wafer is cut intosingle chip packages.

Since the size of the semiconductor chip is decreased and the functionaldensity on the semiconductor chip is increased, the insulating propertyof the chip is one of the important research directions in the chippackaging techniques to avoid erroneous electrical connection.Generally, an epoxy material has advantages of excellent insulatingproperty, low costs and simple process, so it is widely applied toprepare the isolation layer of the chip package. However, the epoxymaterial has flowability and is easily affected by the gravity toaggregate, which is not benefit for forming uniform isolation layer, andthus decreases the yield of the chip package.

SUMMARY

Thus, the present disclosure provides a chip package and a manufacturingmethod thereof to enhance insulating property between internal wires ofthe chip package.

The present disclosure provides a chip package, which includes a chip,an insulating layer, a flowing insulating material layer and conductivelayer. The chip has a conductive pad, a side surface, a first surfaceand a second surface opposite to the first surface, which the sidesurface is between the first surface and the second surface, and theconductive is below the first surface and protruded from the sidesurface. The insulating layer covers the second surface and the sidesurface, and the flowing insulating material layer is disposed below theinsulating layer, and the flowing insulating material layer has a trenchexposing the conductive pad protruded form the side surface. Theconductive layer is disposed below the flowing insulating material layerand extended into the trench to contact the conductive pad.

In various embodiments of the present disclosure, the insulating layerincludes oxide, nitride, oxynitride, or combinations thereof.

In various embodiments of the present disclosure, the insulating layerincludes silicon oxide, silicon nitride, silicon oxynitride, orcombinations thereof.

In various embodiments of the present disclosure, the flowing insulatingmaterial layer includes an epoxy.

In various embodiments of the present disclosure, a thickness of theinsulating layer is in a range from about 0.5 um to about 1.5 um.

In various embodiments of the present disclosure, the flowing insulatingmaterial layer has a thickness of 20 um to 25 um below the secondsurface.

In various embodiments of the present disclosure, the flowing insulatingmaterial layer has a thickness of 6 um to 10 um on the side surface.

In various embodiments of the present disclosure, the chip packagefurther includes a protective layer and an external conductiveconnection. The protective layer is disposed below the conductive layer,and the protective layer has an opening to expose the conductive layer.The external conductive connection is disposed in the opening and incontact with the conductive layer.

In various embodiments of the present disclosure, the chip packagefurther includes a sensing region disposed below the first surface.

In various embodiments of the present disclosure, the chip packagefurther includes a spacer layer and a transparent substrate. The spacelayer is disposed above the first surface to surround the sensingregion, and the transparent substrate is disposed above the space layerto cover the sensing region.

Another aspect of the present disclosure provides a method offabricating a chip package, and the method includes following steps. Awafer is received, which the wafer has a conductive pad, a first surfaceand a second surface opposite to the first surface, and the conductivepad is below the first surface. A portion of the wafer is removed toform a side surface between the first surface and the second surface,and the conductive pad is protruded from the side surface. An insulatinglayer is formed to cover the second surface and the side surface, and aflowing insulating material layer is formed to cover the insulatinglayer and the conductive pad. A trench is formed in the flowinginsulating material layer to expose the conductive pad protruded fromthe side surface, and a conductive layer is formed below the flowinginsulating material layer, which the conductive layer is extended intothe trench to contact the conductive pad.

In various embodiments of the present disclosure, the wafer furtherincludes a sensing region below the first surface.

In various embodiments of the present disclosure, the method furtherincludes following steps. A space layer is formed above the firstsurface to surround the sensing region, and a transparent substrate isformed above the space layer to cover the sensing region.

In various embodiments of the present disclosure, the method furtherincludes following steps. A protective layer is formed below theconductive layer, and an opening is formed in the protective layer toexpose the conductive layer.

In various embodiments of the present disclosure, the method furtherincludes forming an external conductive connection in the opening tocontact the conductive layer.

In various embodiments of the present disclosure, the method furtherincludes dicing the protective layer, the conductive layer, the spacelayer and the transparent substrate along the trench to form the chippackage.

In various embodiments of the present disclosure, the insulating layeris formed by chemical vapor depositing.

In various embodiments of the present disclosure, the flowing insulatingmaterial layer is formed by coating, depositing or printing.

In various embodiments of the present disclosure, the insulating layerincludes oxide, nitride, oxynitride, or combinations thereof.

In various embodiments of the present disclosure, the insulating layerincludes silicon oxide, silicon nitride, silicon oxynitride, orcombinations thereof.

In various embodiments of the present disclosure, the flowing insulatingmaterial layer includes an epoxy.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention can be more fully understood by reading the followingdetailed description of the embodiment, with reference made to theaccompanying drawings as follows:

FIG. 1 is a cross-sectional view of a chip package, in accordance withsome embodiments of the present disclosure.

FIG. 2 illustrates a flow chart of a method of fabricating the chippackage, in accordance with various embodiments.

FIGS. 3A to 3H are cross-sectional views of the chip package in FIG. 1at intermediate stages of fabrication, in accordance with variousembodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The structure may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

FIG. 1 is a cross-sectional view of a chip package 100, in accordancewith some embodiments of the present disclosure. As shown in FIG. 1, thechip package 100 includes a chip 110, a space layer 120, a transparentsubstrate 130, an insulating layer 140, a flowing insulating materiallayer 150, a conductive layer 160, a protective layer 170 and anexternal conductive connection 180. The chip 110 has a conductive pad112, a sensing region 114, a side surface 115, a first surface 116 and asecond surface 117 opposite to the first surface 116. The side surface115 is between the first surface 116 and the second surface 117 toconnect the second surface 117 and the conductive pad 112. Theconductive pad 112 and the sensing region 114 are below the firstsurface 116, and the conductive pad 112 is protruded from the sidesurface 115 of the chip 110. In some embodiments, the sensing region 114is disposed between two conductive pads 112 and electrically connectedto these conductive pads 112. In some embodiments, the chip 110 furtherincludes a semiconductor device, an inter-layer dielectric layer (ILD),an inter-metal dielectric layer (IMD), a passivation layer and aninterconnection structure, and the conductive pad 112 is one of metallayers of the interconnection structure.

The space layer 120 is disposed above the first surface 116 to surroundthe sensing region 114, and the transparent substrate 130 is disposedabove the space layer 120 to cover the sensing region 114. Light isallowed to pass through the transparent substrate 130, and the spacelayer 120 maintains a space between the transparent substrate 130 andthe sensing region 114. In addition, the transparent substrate 130 andspace layer 120 together constitute a cavity to protect the sensingregion 114. Therefore, incident light signal is effectively convertedinto digital signal when the light passes through the transparentsubstrate 130 and reaches the sensing region 114. In some embodiments,an adhesive layer is between the space layer 120 and the first surface116, so as to adhere the space layer 120 to the first surface 116.

The insulating layer 140 covers the second surface 117 and furtherextends to cover the side surface 115, and the flowing insulatingmaterial layer 150 is below the insulating layer 140 and has a trench152 exposing the conductive pad 112 protruded form the side surface 115.Before curing, the flowing insulating material layer 150 hasflowability, so it is easily affected by gravity and difficult tocontrol uniformity thereof. If the flowing insulating material layer 150having a small thickness T1 on the side surface 115, a distance betweenthe conductive layer 160 and the chip 110 will be reduced. Therefore,insulating property of the chip 110 is become worse, and thus increasesthe risks of leakage current. However, a process could be controlled toform the flowing insulating material layer 150 having the sufficientthickness T1 on the side surface 115, but a thickness T2 of the flowinginsulating material layer 150 below the second surface 117 iscorrespondingly increased. During the repeated test of heating andcooling the chip package 100, the flowing insulating material layer 150having great thickness is easily to be cracked due to thermal expansionand contraction, and thus also disconnects the conductive layer 160. Insome embodiments, the flowing insulating material layer 150 has asmallest thickness T1 at a corner 119 between the second surface 117 andthe side surface 115.

To solve above problems, the insulating layer 140 having a thickness T3is interposed between the chip 110 and the flowing insulating materiallayer 150. The insulating layer 140 is formed of low-k dielectricmaterial, which has compact structure and stable property, so as tomaintain excellent insulating property of the chip 110. In addition, theinsulating layer 140 is not flowable, so it could uniformly cover thesecond surface 117 and the side surface 115. As such, even if the smallthickness T1 of flowing insulating material layer 150 on the sidesurface 115 decreases the distance between the conductive layer 160 andthe chip 110, the insulating layer 140 still maintains excellentinsulating property of the chip 110 to ensure it not in contact with theconductive layer 160, and thus avoids the unwanted electricalconnection. On the other hand, an amount of a flowing material is notincreased, so the flowing insulating material layer 150 below the secondsurface 117 is maintained at the appropriate thickness T2. As such, theconductive layer 160 is no longer under the risk of disconnection duringthe repeated test of heating and cooling. It is worth noting that thechip 110 has poor insulating property when the thickness T3 of theinsulating layer 140 is too small, but the insulating layer 140 havinggreat thickness T3 is also adverse for forming the subsequent conductivelayer 160. In some embodiments, the thickness T3 of the insulating layer140 is in a range from about 0.5 um to about 1.5 um, preferably 1 um. Insome embodiments, the flowing insulating material layer 150 has thethickness T1 of 6 um to 10 um on the side surface 115. In someembodiments, the flowing insulating material layer 150 has the thicknessT2 of 20 um to 25 um below the second surface.

In some embodiments, the insulating layer 140 includes an oxide, anitride, an oxynitride, or combinations thereof, which the oxide issilicon oxide, the nitride is silicon nitride, and the oxynitride issilicon oxynitride, but not limited thereto. In some embodiments, theflowing insulating material layer 150 includes an epoxy, such as aphotosensitive epoxy.

In addition, the flowing insulating material layer 150 has a trench 152to expose the conductive pad 112 protruded from the side surface 115,and the trench 152 is further extended into the spacer layer 120. Theconductive layer 160 is disposed below the flowing insulating materiallayer 150 and extended into the trench 152 to contact the conductive pad112. The protective layer 170 is disposed below the conductive layer 160to cover it, and the protective layer 170 has an opening 172 exposingthe conductive layer 160. The external conductive connection 180 isdisposed in the opening 172 and in contact with the conductive layer160. As such, the external conductive connection 180 is electricallyconnected to the sensing region 114 via the conductive layer 160 and theconductive pad 112, so as to deliver the signal of the sensing region114 to an external device, such as a printed circuit board. In someembodiments, the conductive layer 160 includes aluminum, copper, nickelor any suitable conductive material; the protective layer 170 includesan epoxy, such as a photosensitive epoxy; and the external conductiveconnection 180 includes a solder ball, a bump or other well-knownstructures in the industry, and a shape of the external conductiveconnection 180 includes spherical, oval, square or rectangular, but notlimited thereto.

Refer to FIG. 2, which illustrates a flow chart of a method offabricating the chip package, in accordance with various embodiments.Refer to FIGS. 3A to 3H at the same time to further understand thefabricating process of the chip package. FIGS. 3A to 3H arecross-sectional views of the chip package in FIG. 1 at intermediatestages of fabrication, in accordance with various embodiments.

Refer first to step 210 and FIG. 3A, a wafer 300 is received, which hasa conductive pad 112, a first surface 116 and a second surface 117opposite to the first surface 116, which the conductive pad 112 is belowthe first surface 116. Specifically, the wafer 300 has a plurality ofchip districts, and these chip districts are separated to independentchip packages 100 after dicing the wafer 300 in the subsequent step. Insome embodiments, the wafer 300 includes a semiconductor device, aninter-layer dielectric layer (ILD), an inter-metal dielectric layer(IMD), a passivation layer and an interconnection structure, and theconductive pad 112 is one of metal layers of the interconnectionstructure. In some embodiments, the wafer 300 further includes a sensingregion 114 disposed between two conductive pads 112 and electricallyconnected to these conductive pads 112. Continuing in step 220 and FIG.3A, a spacer layer 120 is formed above the first surface 116 to surroundthe sensing region 114, and then a transparent substrate 130 is formedabove the spacer layer 120 to cover the sensing region 114.

Refer to step 230 and FIG. 3B, a portion of the wafer 300 is removed toform a side surface 115 between the first surface 116 and the secondsurface 117, and the conductive pad 112 is protruded from the sidesurface 115. In this step, the portion of the wafer 300 is removed byphotolithography etching, so as to form an opening 118 in the wafer 300to expose the conductive pad 112. Specifically, the opening 118 isformed to make the wafer 300 have the side surface 115 connecting theconductive pad 112 and the second surface 117, and a potion of theconductive pad 112 is protruded from the side surface 115 and exposed inthe opening 118.

Refer to step 240 and FIG. 3C, an insulating layer 140 is formed tocover the second surface 117 and the side surface 115. In this step, alow-k dielectric material is deposited on the second surface 117 and theside surface 115 by using chemical vapor deposition (CVD), so as to formthe insulating layer 140. Since low-k dielectric material has lowflowability, it will not be affected by gravity, so the insulating layer140 has a uniform thickness T3. In some embodiments, the thickness T3 ofthe insulating layer 140 is in a range from about 0.5 um to about 1.5um, preferably 1 um.

Continuing to step 250 and FIG. 3D, a flowing insulating material layer150 is formed to cover the insulating layer 140 and the conductive pad112. In this step, the flowing insulating material layer 150 is formedon the second surface 117 and in the opening 118 by coating, depositingor printing, so as to cover the spacer layer 120 and the conductive pad112 exposed in the opening 118. It is worth noting that the flowinginsulating material layer 150 has flowablity before curing, so a portionof the flowing insulating material layer 150 on the side surface 115 isaffected by gravity and flows toward a bottom of the opening 118. Assuch, the flowing insulating material layer 150 has a thickness T1 onthe side surface 115 and a thickness T2 below the second surface 117,and the thickness T1 is smaller than the thickness T2. However, theinsulating layer 140 covering the side surface 115 still maintainsexcellent insulating property of the wafer 300. In some embodiments, theflowing insulating material layer 150 has the smallest thickness T1 at acorner 119 between the second surface 117 and the side surface 115. Insome embodiments, the flowing insulating material layer 150 includes anepoxy, such as a photosensitive epoxy, so an exposure process is furtherperformed to crosslink and cure the flowing insulating material layer150.

Continuing in step 260 and FIG. 3E, a trench 152 is formed in theflowing insulating material layer 150 to expose the conductive pad 112protruded from the side surface 115. In this step, a knife is used tocut off a portion of the flowing insulating material layer 150, a potionof the conductive pad 112 and a portion of the spacer layer 120, so asto form the trench 152 exposing the conductive pad 112 protruded fromthe side surface 115.

Continuing in step 270 and FIG. 3F, a conductive layer 160 is formedbelow the flowing insulating material layer 150, and the conductivelayer 160 is extended into the trench 152 to contact the conductive pad112. For example, a conductive material is deposited by sputtering,evaporating, electroplating or electroless plating to form theconductive layer 160. As aforementioned, even if the small thickness T1of the flowing insulating material layer 150 on the side surface 115decreases the distance between the conductive layer 160 and the sidesurface 115 of the chip 110, the insulating layer 140 still maintainsexcellent insulating property to avoid the leakage current. In addition,the flowing insulating material layer 150 is directly cut by the knifeto form the trench 152 exposing the conductive pad 112, and thus furthersaves the costs of exposing and developing the flowing insulatingmaterial layer 150. In some embodiments, the conductive layer 160includes aluminum, copper, nickel or any suitable conductive material.

Continuing in step 280 and FIG. 3G, a protective layer 170 is formedbelow the conductive layer 160, and an opening 172 is formed in theprotective layer 170 to expose the conductive layer 160. In this step,an epoxy material is brush-coated below the conductive layer 160 to formthe protective layer 170. Then, the protective layer 170 is pattered toform the opening 172, so as to expose a portion of the conductive layer160 from the opening 172 of the protective layer 170. In the presentdisclosure, the protective layer 170 is formed of a photosensitiveepoxy, which is directly photolithography etched to pattern theprotective layer 170 and form the opening 172, so the pattern of theprotective layer 170 could be defined without using a photoresist layer.In some embodiments, the protective layer 170 and the flowing insulatingmaterial layer 150 are formed of the same material, but not limitedthereto.

Continuing in step 290 and FIG. 3H, an external conductive connection180 is formed in the opening 172 to contact the conductive layer 160,and the wafer 300 is diced along the trench 152 to form the chippackage. The external conductive connection 180 includes a solder ball,a bump or other well-known structures in the industry, and a shape ofthe external conductive connection 180 includes spherical, oval, squareor rectangular, but not limited thereto. After forming the externalconductive connection 180, the protective layer 170, the conductivelayer 160, the spacer layer 120 and the transparent substrate 130 aredice along a scribe line 310 in the trench 152, so as to separate thechip districts of the wafer 300, and the independent chip package isformed. In the present disclosure, the scribe line 310 is in the trench152.

The embodiments of the present disclosure discussed above haveadvantages over existing methods and structures, and the advantages aresummarized below. A chip package of the present disclosure has aninsulating layer interposed between the chip and the flowing insulatingmaterial layer. The insulating layer ensures excellent insulatingproperty of the chip, so as to avoid the conductive layer contacting thechip and generating unwanted electrical connection. In addition, thepresent disclosure enhances the insulating property of the chip withoutincreasing a thickness of the flowing insulating material layer. Assuch, it is avoided that the flowing insulating material layer havinggreat thickness is cracked under the a test of heating and cooling thechip package, meanwhile the conductive layer is no longer under the riskof disconnection, and thus significantly increases the yield andreliability of the chip package. On the other hand, before a dicingprocess for the chip package is utilized, processes performed on thewafer are with a wafer level, so that the manufacturing cost of the chippackage is lower than a conventional wire-bonding process. Moreover,after the cutting process, the chip package is a chip scale package(CSP), thereby facilitating the miniaturization design of the chippackage.

Although the present invention has been described in considerable detailwith reference to certain embodiments thereof, other embodiments arepossible. Therefore, the spirit and scope of the appended claims shouldnot be limited to the description of the embodiments contained herein.Reference will now be made in detail to the embodiments of theinvention, examples of which are illustrated in the accompanyingdrawings. Wherever possible, the same reference numbers are used in thedrawings and the description to refer to the same or like parts.

What is claimed is:
 1. A chip package, comprising: a chip having aconductive pad, a side surface, a first surface and a second surfaceopposite to the first surface, the side surface being between the firstsurface and the second surface, and the conductive being below the firstsurface and protruded from the side surface; an insulating layercovering the second surface and the side surface; a flowing insulatingmaterial layer disposed below the insulating layer, and the flowinginsulating material layer having a trench exposing the conductive padprotruded form the side surface; and a conductive layer disposed belowthe flowing insulating material layer and extended into the trench tocontact the conductive pad.
 2. The chip package of claim 1, wherein theinsulating layer comprises oxide, nitride, oxynitride, or combinationsthereof.
 3. The chip package of claim 2, wherein the insulating layercomprises silicon oxide, silicon nitride, silicon oxynitride, orcombinations thereof.
 4. The chip package of claim 1, wherein theflowing insulating material layer comprises an epoxy.
 5. The chippackage of claim 1, wherein a thickness of the insulating layer is in arange from about 0.5 um to about 1.5 um.
 6. The chip package of claim 1,wherein the flowing insulating material layer has a thickness of 20 umto 25 um below the second surface.
 7. The chip package of claim 1,wherein the flowing insulating material layer has a thickness of 6 um to10 um on the side surface.
 8. The chip package of claim 1, furthercomprising: a protective layer disposed below the conductive layer, andthe protective layer having an opening to expose the conductive layer;an external conductive connection disposed in the opening and in contactwith the conductive layer.
 9. The chip package of claim 8, wherein thechip further comprises a sensing region disposed below the firstsurface.
 10. The chip package of claim 9, further comprising: a spacelayer disposed above the first surface to surround the sensing region;and a transparent substrate disposed above the space layer to cover thesensing region.
 11. A method of fabricating a chip package, the methodcomprising: receiving a wafer, the wafer having a conductive pad, afirst surface and a second surface opposite to the first surface, andthe conductive pad being below the first surface; removing a portion ofthe wafer to form a side surface between the first surface and thesecond surface, and the conductive pad being protruded from the sidesurface; forming an insulating layer to cover the second surface and theside surface; forming a flowing insulating material layer to cover theinsulating layer and the conductive pad; forming a trench in the flowinginsulating material layer to expose the conductive pad protruded fromthe side surface; and forming a conductive layer below the flowinginsulating material layer, and the conductive layer extended into thetrench to contact the conductive pad.
 12. The method of fabricating thechip package of claim 11, wherein the wafer further comprises a sensingregion below the first surface.
 13. The method of fabricating the chippackage of claim 12, further comprising: forming a space layer above thefirst surface to surround the sensing region; and forming a transparentsubstrate above the space layer to cover the sensing region.
 14. Themethod of fabricating the chip package of claim 13, further comprising:forming a protective layer below the conductive layer; and forming anopening in the protective layer to expose the conductive layer.
 15. Themethod of fabricating the chip package of claim 14, further comprisingforming an external conductive connection in the opening to contact theconductive layer.
 16. The method of fabricating the chip package ofclaim 15, further comprising dicing the protective layer, the conductivelayer, the space layer and the transparent substrate along the trench toform the chip package.
 17. The method of fabricating the chip package ofclaim 11, wherein the insulating layer is formed by chemical vapordeposition.
 18. The method of fabricating the chip package of claim 11,wherein the flowing insulating material layer is formed by coating,depositing or printing.
 19. The method of fabricating the chip packageof claim 11, wherein the insulating layer comprises oxide, nitride,oxynitride, or combinations thereof.
 20. The method of fabricating thechip package of claim 19, wherein the insulating layer comprises siliconoxide, silicon nitride, silicon oxynitride, or combinations thereof. 21.The method of fabricating the chip package of claim 11, wherein theflowing insulating material layer comprises an epoxy.